Autors: Spasova, M. L., Angelov, G. V., Hristov, M. H.
Title: Simulation of 1T DRAM Memory Cell with Verilog-A Model of CNTFET in Cadence
Keywords: Carbon nanotubes, CNTFET, 1T DRAM, compact model, circuit simulation

Abstract: Carbon nanotubes are promising materials for the nanoscale memory devices. A Verilog-A formulation of the Stanford compact model for CNTFET is used for simulation of 1T DRAM cell in Cadence Spectre circuit simulator. Read and write operations of the 1T DRAM circuit with CNTFET are compared to the memory circuit with standard nmos4 transistor from 0.35 m CMOS design kit of AMS. The analysis showed that CNTFET is applicable to 1T DRAM memory cell and CNTFET memory cell has better performance compared to the standard MOSFET.


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Annual J. of Electronics, vol. 6, issue 2, 2012, Bulgaria, TU-Sofia, ISSN 1314-0078

Full text of the publication

Цитирания (Citation/s):
1. P. Saha, S. Basak and S. K. Sarkar, "Performance analysis of a high speed, energy efficient 4×4 dynamic RAM cell array using 32nm fully depleted SOI/SON and CNFET," 2014 Recent Advances in Engineering and Computational Sciences (RAECS), Chandigarh, India, 2014, pp. 1-6, DOI: 10.1109/RAECS.2014.6799532 - 2014 - в издания, индексирани в Scopus или Web of Science

Вид: публикация в международен форум