Autors: Spasova, M. L., Angelov, G. V., Hristov, M. H.
Title: Design of 1T DRAM memory cell using Verilog-A model of high-k MOS capacitor in Cadence
Keywords: High-k gate dielectric, HfO2-Ta2O5, DRAM, compact model, circuit simulation

Abstract: A Verilog-A model of high-k MOS capacitor made of HfO2-Ta2O5 stack is simulated in an 1T DRAM cell circuit in Cadence circuit simulator Spectre. Read and write operations of the 1T DRAM circuit with high-k and standard Cpoly capacitors are compared to each other. The high-k capacitor shows better performance and applicability to memory cell circuits.

References

    Issue

    Annual Journal of Electronics, vol. 5, issue 2, pp. 135-138, 2011, Bulgaria, ISSN 1313-1842

    Full text of the publication

    Вид: статия в списание, публикация в реферирано издание