|Autors: Spasova, M. L., Angelov, G. V., Hristov, M. H.|
Title: Design of 1T DRAM memory cell using Verilog-A model of high-k MOS capacitor in Cadence
Keywords: High-k gate dielectric, HfO2-Ta2O5, DRAM, compact model, circuit simulation
Abstract: A Verilog-A model of high-k MOS capacitor made of HfO2-Ta2O5 stack is simulated in an 1T DRAM cell circuit in Cadence circuit simulator Spectre. Read and write operations of the 1T DRAM circuit with high-k and standard Cpoly capacitors are compared to each other. The high-k capacitor shows better performance and applicability to memory cell circuits.
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