|Autors: Brusev, T. S., Uzunov, I. S., Kunov, G. T., Gadjeva, E. D.|
Title: Investigation of Parallel Hybrid CMOS Envelope Amplifier Designed on AMS 0.35 μm Proces
Keywords: envelope amplifier, Cadence, efficiency, 4G LTE, CMOS technology
Abstract: Customer demands for battery powered portable electronic devices have increased. Today high data rates could be transmitted using fourth generation Long-Term Evolution (4G LTE) wireless communications standard. To increase system run-time proper envelope amplifier’s architecture has to be selected. Using envelope tracking technique efficiency of the transmitter’s power amplifier (PA) can be improved. In this paper different circuit architectures of envelope amplifier are considered. Parallel combined hybrid structure is designed using CMOS 0.35 µm technology. Switching-mode buck converter operates with switching frequency fs up to 80 MHz to address the wide bandwidth of LTE envelope. The maximum simulated efficiency of the envelope amplifier is 79. 8 %.
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