|Autors: Mollov, V. S.|
Title: CMOS Three-State Buffer Delay Optimization for High Speed Implementation
Keywords: buffers, three-state, delay optimization, CMOS, LT Spice, transmission line
Abstract: The paper discusses the nature of the inherent dynamic delays in most popular three-state CMOS buffer stage. We analyze the origin of the 3-state disable and enable times at transistor level and how it could be optimized using pull-up and pull-down driver transistors or simply resizing of the output transistors. Some simulation with LTSpice are prepared for several loads as well as measurements with 74HCT244 buffer are done, as well.
Вид: публикация в международен форум, публикация в реферирано издание