|Autors: Brusev, T. S., Hristov, M. H.|
Title: Power Losses in Monolithic Buck DC-DC Converter Designed on CMOS 0.35 µm Technology
Keywords: Monolithic buck dc-dc converter, Power losses, Cadence, CMOS 0.35 µm technology.
Abstract: This paper includes investigations of power losses in monolithic buck dc-dc converter designed with Cadence on CMOS 0.35 µm process. Input voltage of the designed circuit is equal to 3.6 V and output voltage is regulated to 1.2 V. Evaluated and estimated are power dissipations in the MOS transistor, filter inductor and filter capacitor of the buck converter. Investigated and compared are losses in the off-chip filter inductors of the company Murata and on-chip filter inductors. For the extraction of the model’s parameters of integrated inductors CMOS 0.35 µm process is used “Virtuoso Passive Component Designer”.
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