Детайли за публикацията
(Publication details)

Autors: Spasova, M. L., Brusev, T. S., Angelov, G. V., Radonov, R. I., Hristov, M. H.
Title: Low Power Ramp Generator with MOSFET and CNTFET Transistors
Keywords: CNTFET transistor; ramp generator; buck dc-dc converter; power losses, efficiency, Cadence Spectre

Abstract: In this paper we compare low power ramp generator schematics realized with conventional MOSFET transistors and CNTFET transistors. The current consumption and power losses of the both circuits are evaluated and analyzed. The generator circuit is part of an overall buck dc-dc converter system, which uses a PWM control technique. The investigation is performed in Cadence Spectre circuit simulator using the 0.35 µm CMOS technology design kit.

References

  1. M. Alhawari, D. Kilani, B. Mohammad, H. Saleh and M. Ismail, "An efficient thermal energy harvesting and power management for μWatt wearable BioChips", 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, pp. 2258-2261, 2016.
  2. A. Paidimarri and A. P. Chandrakasan, "A Wide Dynamic Range Buck Converter With Sub-nW Quiescent Power", in IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3119-3131, Dec. 2017.
  3. A. Roy, A. Klinefelter, F. B. Yahya, X. Chen, L. P. Gonzalez-Guerrero, C. J. Lukas, D. A. Kamakshi, J. Boley, K. Craing, M. Faisal, S. Oh, N. E. Roberts, Y. Shakhsheer, A. Shrivastava, D. P. Vasudevan, D. D. Wentzloff, and B. H. Calhoun, “A 6.45 μW self-powered SoC with integrated energy-harvesting power management and ULP asymmetric radios for portable biomedical systems”, IEEE Trans. Biomed. Circuits Syst., vol.9, no. 6 pp. 862-874, Dec. 2015.
  4. Y. J. Park, J. H. Park, H. J. Kim, H. Ryu, S. Y. Kim, "A Design of a 92.4% Efficiency Triple Mode Control DC–DC Buck Converter with Low Power Retention Mode and Adaptive Zero Current Detector for IoT/Wearable Applications", IEEE Transactions on Power Electronics, vol. 32, no. 9, pp. 6946-6960, Sept. 2017.
  5. Stanford CNFET Model. https://nano.stanford.edu/stanford-cnfet-model
  6. M. Spasova, Angelov G., Dobrichkov B., Gadjeva E. and Hristov M., “DRAM design based on carbon nanotube field effect transistors”, 39th International Spring Seminar on Electronics Technology (ISSE), pp. 372 - 377, 2016.
  7. M. Spasova, Nikolov D., Angelov G., Radonov R., Hristov М., "SRAM design based on carbon nanotube field effect transistor's model with modified parameters", 40th International Spring Seminar on Electronics Technology (ISSE), pp. 1-4, 2017.

Issue
2019 IEEE XXVIII International Scientific Conference Electronics (ET), 2019, Bulgaria, ISBN 978-1-7281-2574-9

Вид: постер/презентация в международен форум, индексирана в Scopus

Въведена от: доц. д-р Росен Иванов Радонов