|Autors: Dimitrievski, I. M., M, V. S.|
Title: Performance testing methods for NoC-based smart Ethernet switches
Keywords: Performance, evaluation, ns2, latency, throughput
Abstract: The problem for effective prototyping of the Networks on Chip (NoC) based devices has become an important issue since they have started to be implemented in high-performance smart switches single-chip devices. Now, the NoC-based switches are required to fulfill the requirements for excellent performance as lowest possible time delay and overall latency, an increased traffic speed through the network switch, and also an increased bandwidth and throughput. In this paper the state-of-the-art methods for NoC prototyping are presented. Some platforms used for prototyping of these networks are discussed: with a hardcoded core and reconfigurable FPGA part and with a fully configurable FPGA architecture. An overview of the selected platforms is done with an introduction to Ethernet switch simulations methods using ns-2 network simulator.
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Вид: постер/презентация в национален форум, индексирана в Google Scholar
Въведена от: докт. д-р Иле Димитриевски