Autors: Hristov, M. H., Kuncheva, S, A., Mougel, T., Fujcik, L., Donchev, B.
Title: DESIGN OF A DECIMATION FILTER FOR NOVEL SIGMA-DELTA MODULATOR
Keywords: ΣΔ modulation, decimation filter, A/D conversion, oversampling, FPGA, VHDL

Abstract: The steps involved in the design of decimation filter for high-resolution sigma-delta (ΣΔ) A/D converter are described. The design of a decimation filter is proposed that employs three stage – one Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This approach eliminates the need for multiplication, requires a maximum clock frequency equal to the sampling. Specifications of decimation filter are dependent upon the overall specification from ΣΔ A/D converter with sampling frequency 16 MHz. The design implements a decimation ratio of 64, allows a

References

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Issue

ELECTRONICS’ 2005,21 – 23 September, vol. 5, pp. 56-61, 2005, Bulgaria,

Вид: пленарен доклад в международен форум