Autors: Kralev J.K., Petkov, P. H.
Title: Design of UART controller for FPGA with Simulink
Keywords: FPGA design flow, Simulink, HDL coder, digital system simula

Abstract: Simple UART (Universal Asynchronous Receiver Transmitter) controller, compatible with RS232 standard is implemented on Spartan-3E FPGA, through automatic HDL code generation and hardware synthesis. The paper shows how the design can be entirely conveyed in MATHLAB/Simulink environment.



    3rd Mediterranean Conference on Embedded Computing, pp. 44-47, 2014, Montenegro, IEEE

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    Вид: публикация в международен форум, индексирана в Scopus