Autors: Rusev, R. P., Ruskova, I. N., Angelov, G. V., Nikolov, D. N., Gieva, E. E., Radonov, R. I., Minkov, D. A.
Title: TCAD model of GAA Nanowire Transistor with silicon oxide/nitride/oxide dielectric
Keywords: TCAD, silicon nanowire, COMSOL modelling

Abstract: By reducing the size of transistors, their integration increases, their consumption decreases, but undesirable short-channel effects occur in them. To avoid these effects, junctionless JLFETs, which are composed of a single nanowire (NW), have been developed. The device layer is fully depleted when the gate voltage is lower than the threshold voltage when the gate voltage is increased, so electrons are attracted towards the oxide/semiconductor interface, and the depletion region width is reduced, thus a channel between the source and the drain below the depletion region is created, and a bulk current flows. The doping of the channel, its length, the work function of the gate electrode and the material of the gate dielectric are important parameters [1-4]. Technology computer-aided design (TCAD) models can give us advantages for device operation of JL FET depending on the above design parameters. The effect of a three-layer subgate dielectric on transistor performance is investigated.

References

  1. Rassekh, A., Fathipour, M. A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET. J Comput Electron 19, 631–639 (2020). https://doi.org/10.1007/s10825-020-01475-9
  2. Mohammad Bavir, Abdollah Abbasi, Ali Asghar Orouji, Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications, Journal of Electronic Materials, 10.1007/s11664-022-09462-5, 51, 5, (2083-2094), (2022).
  3. D. Gola, B. Singh, J. Singh, S. Jit and P. K. Tiwari, "Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects," in IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 2876-2883, July 2019, doi: 10.1109/TED.2019.2915294
  4. S. -J. Choi et al., "Nonvolatile Memory by All-Around-Gate Junctionless Transistor Composed of Silicon Nanowire on Bulk Substrate," in IEEE Electron Device Letters, vol. 32, no. 5, pp. 602-604, May 2011, doi: 10.1109/LED.2011.2118734

Issue

47th International Spring Seminar on Electronics Technology (ISSE), pp. 1-4, 2024, Czech Republic,

Цитирания (Citation/s):
1. Rajesh G., Adinarayana T.V.S., Harshavardhan P.R., Niranjan Sharma S.H., Analysis of Gate-All-Around FETs Using Si, SiC, and GaN for Advanced Logic Applications, 2025, Proceedings of 2025 IEEE International Conference on Contemporary Computing and Communications Inc4 2025, issue 0, DOI 10.1109/InC465408.2025.11256216 - 2026 - в издания, индексирани в Scopus

Вид: публикация в международен форум, публикация в реферирано издание, индексирана в Scopus и Web of Science