Autors: Malaj, E. G., Marinova, G. I.
Title: Effect of the Hardware Logical Encryption Type and Location on the Corruption Factor
Keywords: Performance evaluation;VHDL;Logic gates;Hardware;Logic encry

Abstract: Logical encryption hides functionality by implementing modifications to the circuit design. Inside the original design are inserted additional logic gates where the key entry bits are affected. The circuit works correctly only with a valid key. In this paper 3 types of hardware encryption logic (XOR/XNOR-based, MUX-based and Encrypt D-flip-flop technique) are studied using an experimental setup to measure the security level determining the Hamming Distance (HD), the corruption and deceptiveness factors. The experimental setup is based on VHDL descriptions of original and encrypted circuits. The simulation of the experimental setup resulting in the identification of the wrong bits is performed on Zedboard (family of ZYNQ 7000 field-programmable gate array FPGA devices) and Viv ado software (version 2014.2). Neither the key nor the functionalities of the circuit should be revealed from the structural or functional analysis of the encrypted netlist. The paper studies the influence of the

References

    Issue

    2023 IEEE International Workshop on Technologies for Defense and Security, TechDefense 2023, pp. 331–335, 2023, Italy, IEEE Xplore, DOI oi: 10.1109/TechDefense59795.2023.10380923

    Copyright IEEE

    Вид: публикация в международен форум, публикация в реферирано издание, индексирана в Scopus и Web of Science