| Autors: Stoyanov, S. I., Kakanakov, N. R., Marinova, M. P. Title: Secure Heterogeneous Architecture based on RISC-V and root-of-trust Keywords: Security and privacy, Security in hardware, Hardware securit Abstract: This paper describes the architecture and development of a secure heterogeneous RISC-V system with protection dedicated core that provides hardware mechanisms for establishing root-of-trust, monitoring and controlling the execution of the rest of the cores in the system. The focus is on the security core which serves as control unit for the rest of the computational processors. References Issue
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Цитирания (Citation/s):
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2. Perkins G., Macht B., Ritzdorf L., Crane T.R., Lameres B., Izurieta C., Reinhold A.M., SoK: Trusted Execution in SoC-FPGAs, 2025, 2025 Intermountain Engineering Technology and Computing Ietc 2025, issue 0, DOI 10.1109/IETC64455.2025.11039468 - 2025 - в издания, индексирани в Scopus
3. Kannaiah K., Jogi S., Reddy B.N.K., Adaptive Hardware-Assisted Data-Flow Integrity for Secure RISC-V IoT Devices, 2026, Proceedings of the National Academy of Sciences India Section A Physical Sciences, issue 0, DOI 10.1007/s40010-026-01157-4, issn 03698203, eissn 22501762 - 2026 - в издания, индексирани в Scopus
Вид: пленарен доклад в международен форум, публикация в реферирано издание, индексирана в Scopus