Autors: Mollov, V. S.
Title: Combined approach for evaluation and calculation of CMOS logic circuits timing capabilities
Keywords: CMOS, measurement, timing parameters, parasitic capacitances

Abstract: Here, a comprehensive and easy to apply engineering approach is presented which allows the timing capabilities of CMOS gates to be evaluated by measurements and simple calculations. The focus is on the values of the propagation delays of a single inverter stage and the origin of its load and parasitic capacitances.Based on the measured values for a single gate we can calculate the parasitic capacitances of any fabrication process.

References

    Issue

    Proceedings of the Union of Scientists in Bulgaria-Plovdiv, vol. XVIII, pp. 112-115, 2018, Bulgaria, Union of Scientists in Bulgaria-Plovdiv, ISSN 1311-9192

    Вид: публикация в национален форум