Autors: Badarov, D. H., Mihov, G. S.
Title: FPGA Implementation of All Digital Phase Locked Loop for ADC Synchronization with the Mains Frequency
Keywords: ADC, FPGA, dual slope, ADPLL, mains interference suppression

Abstract: One of the most accurate Analog-to-Digital converters are of the integrating type. Their measurement speed is low but they have high precision. One of the important features in the laboratory environment is the ability to suppress the mains frequency interference signals. If the first integration phase is with period multiple of the mains period the interference is completely suppressed. A completely digital Phase Locked Loop is designed to provide the converter with clock frequency exactly multiple of the mains frequency. The whole system is implemented on FPGA programmable logic device.



    12th National Conference with International Participation, ELECTRONICA 2021, 2021, Bulgaria,

    Вид: постер/презентация в национален форум с межд. уч., индексирана в Scopus