Autors: Stanoeva, M., Popov, A. N.
Keywords: parallel CMOS ADC, dynamic hysteresis

Abstract: A parallel analogue-to-digital converter architecture is investigated, which is based on CMOS inverters used as comparators. The comparator threshold voltage depends on the ratio of transistor areas. A stage with a so-called “dynamic hysteresis” is added to the design to increase the noise immunity. The advantages of such ADC are its fully digital structure, the lack of resistor ladder and the asynchronous mode of operation, which diminishes both area and power and makes it suitable for system-on-chip solutions. The static and dynamic characteristics of the device are examined and some


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